The invention relates to a counter circuit, comprising an end-around coupled chain of n bit stages, an inversion element which is included in the chain in order to form a counter having 2n valid counter positions, and a correction mechanism for forming a valid counter position from an invalid counter position. A counter circuit of this kind is also known as a Johnson counter with error correction; see the article "Error correction in Johnson counters" by P.M.Overfield in New Electronics, Vol. 13, No 11, 27/5/1980, p 38. The n bit stages of a Johnson counter (without error correction) are qenerally connected in series and coupled end-around via an inversion element. External events or a clock signal which is synchronous or not, determine when the counter changes over from one counter position to the next. Starting from a valid initial counter position in which, for example all bit stages have the value zero, the counter successively assumes all 2n valid counter positions before returning to the initial counter position again. These valid counter positions are characterized in that at the most one 1--0 or 0--1 transition occurs between two successive bit stages, ignoring a transition, if any, at the inversion element. When an invalid counter position occurs in the counter, for example due to a power failure, a valid counter position can never be reached again in the absence of a correction mechanism. Therefore, Overfield has extended the Johnson counter with a correction mechanism which also takes into account the end-around coupling via the inversion element. Within 2n counter position transitions, this correction mechanism corrects an invalid counter position so that a valid counter position is obtained.
It is a drawback of this Johnson counter with correction mechanism that any invalid counter position occurring is corrected but not detected; it does not involve a separate signal which occurs exclusively in the case of an invalid counter position and for an arbitrary value of n such a signal cannot be simply derived either from the circuit. The detection of invalid counter positions is very useful in view of the correction of errors stemming from the occurrence of invalid counter positions.